Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
License
Artistic License, GNU General Public License version 2.0 (GPLv2)Follow Verilator
Other Useful Business Software
Auth for GenAI | Auth0
Easily implement secure login experiences for AI Agents - from interactive chatbots to background workers with Auth0. Auth for GenAI is now available in Developer Preview
Rate This Project
Login To Rate This Project
User Reviews
Be the first to post a review of Verilator!